Assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects. This article explains ...

Assertions may also be used as a formal specification language, making the requirements clear and unambiguous, and making it possible to automate validation of the design against the specification.

Jeda is also providing a bidirectional SystemVerilog-to-NSCa assertion translator and an OCP-IP checker with compliance checks for the OCP-IP bus protocol. It's quite a change for the Los Altos, Calif ...